1. Field of the Invention
The present invention relates to a semiconductor memory device and its fabrication and operation.
2. Description of the Related Art
Semiconductor memory devices can be classified into volatile memory devices and non-volatile memory devices. Volatile memory devices cannot retain data without a continuous supply of power. One representative volatile memory device is a dynamic random access memory (DRAM). On the other hand, non-volatile memory devices can retain stored data even without power. A flash memory is an example of a non-volatile memory device.
Conventional volatile and non-volatile memory devices are in a complementary relationship. Recently, attraction for a memory device having the advantages of both the volatile memory device and the non-volatile memory device is increasing. As a result, various types of memory devices have been introduced. FIG. 1 illustrates one conventional memory device introduced recently. This is a ferroelectric random access memory (FRAM) with a cob structure including a ferroelectric capacitor formed on a bit line.
Referring to FIG. 1, a transistor Tr is formed to a semiconductor substrate 10. A first interlayer insulating layer 18 is formed on the substrate 10. The first interlayer insulating layer 18 covers a gate 16 of the transistor Tr. A portion of the first interlayer insulating layer 18 is removed to form a first contact hole 20 exposing a source region 12 of the transistor Tr. A bit line 22 is formed on the first interlayer insulating layer 18, filling the first contact hole 20. A second interlayer insulating layer 24 covering the bit line 22 is formed on the first interlayer insulating layer 18 and the bit line 22. A second contact hole 25 exposing a drain region 14 is formed by penetrating the first interlayer insulating layer 18 and the second interlayer insulating layer 24. The second contact hole 25 is filled with a conductive plug 26. A bottom electrode 28 covering the conductive plug 26 is formed on the second interlayer insulating layer 24. The bottom electrode 28 is covered with a lead-zirconate-titanate (PZT) layer 30. The PZT layer 30 is covered with a top electrode 32. The bottom electrode 28, the PZT layer 30 and the top electrode 32 compose a ferroelectric capacitor. A third interlayer insulating layer 34 covering the ferroelectric capacitor is formed on the second interlayer insulating layer 24. A plate line 36 connected to the top electrode 32 is formed on the third interlayer insulating layer 34.
The memory device has the characteristics of volatile memory device having one transistor and one capacitor, that is, a DRAM structure, and replaces the capacitor with a ferroelectric capacitor, thereby also gaining advantages of a non-volatile memory device.
However, since the conventional memory device is capable of writing only one bit of data per cell, the integration scale of data per cell is limited.